1. Field of the Invention
This invention relates to a power circuit and, more particularly, that useful when applied in using a low ESR (equivalent series resistance) capacitor as an output capacitor.
2. Description of the Related Art
FIG. 11 is a block diagram showing the whole of a step-down DC-DC converter, which is one of representative power circuits. As shown in the drawing, an error amplifier 1 makes a comparison between a reference voltage VREF, which represents a preset voltage value, and a feedback signal FB, and delivers an error signal S1 which represents a deviation between VREF and FB. The feedback signal FB is obtained by dividing an output voltage VOUT by feedback resistances Rfb1 and Rfb2.
A comparator 2 compares the error signal S1 with an output signal S2 of a circuit 3, which generates a triangular wave, and sends out a duty signal S3 which determines the duty ratio of the output voltage VOUT of the DC-DC converter, namely, an output voltage value. The duty signal S3 controls the ON-OFF times of a P-channel MOS transistor P1 and an N-channel MOS transistor N1 via an output buffer circuit 6. This control determines the value of the output voltage VOUT based on an input voltage VIN.
A reactance L0 and an output capacitor CL having an equivalent series resistance component RESR function to smooth the output voltage VOUT.
A phase compensation circuit 7 makes the phase compensation of the error amplifier 1. As FIG. 12, which is an extracted view of portions in the neighborhood of the phase compensation circuit 7, shows in detail, the phase compensation circuit 7 consists of a resistance Rz and a capacitor Cz connected in series, and is connected to the output side of the error amplifier 1 which is a transconductance amplifier.
The DC-DC converter in the above configuration manages a gain Az and a zero-point frequency fz (frequency at a point where the phase returns by 45 degrees) in the high frequency region of the error amplifier 1, and combines these parameters with a zero-point frequency fzfb which is determined by the capacitance of a feedback capacitor Cfb connected in parallel with the feedback resistance Rfb1 determining the output voltage VOUT, thereby dealing with abnormal oscillations.
The above parameters Az, fz, and fzfb are expressed by the following equations (1), (2) and (3):
                    Az        =                  gm          ×          Rz                                    (        1        )                                fz        =                  1                      2            ⁢            π            ×            Cz            ×            Rz                                              (        2        )                                fzfb        =                  1                      2            ⁢            π            ×            Cfb            ×            Rfb            ⁢                                                  ⁢            1                                              (        3        )            
FIG. 13 shows a Bode diagram on the output side of the error amplifier 1 drawn when phase compensation was performed by the phase compensation circuit 7 shown in FIG. 12.
FIG. 14 is a circuit diagram showing another example of the phase compensation circuit 7. The gain Az and the zero-point frequency fz in this case are expressed by the following equations (4) and (5):
                    Az        =                  -                                    R              ⁢                                                          ⁢              2                                      R              ⁢                                                          ⁢              1                                                          (        4        )                                fz        =                  1                      2            ⁢            π            ×            Cz            ×            R            ⁢                                                  ⁢            2                                              (        5        )            
With a voltage regulator using a three-stage amplification method according to a conventional technology shown in FIG. 15, on the other hand, phase compensation is performed based on the frequency of a pole at each amplification stage, and a zero-point frequency fzfb determined by a feedback resistance Rfb1 and a feedback capacitor Cfb.
Assume here that the gain Az and phase are to be set so that the voltage regulator does not oscillate. For this purpose, the zero-point frequency fzfb needs to be set in the vicinity of the frequency of the second pole, at which the phase lags by 180°, whereby phase compensation is carried out. Also, the frequency of the third pole needs to be set at such a high frequency as not to influence, in terms of phase, a crossover frequency f0 at which the total gain of the voltage regulator is zero. However, in consideration of the Tr size of an output Pch driver 8 of the 3rd amplifier, the 2nd amplifier needs to drive a very great load capacitance. Moreover, the 3rd amplifier depends on an output impedance RL and a load capacitance CL external to an IC constituting the voltage regulator and, thus, its pole cannot be set at a high frequency. Hence, the pole of the 1st amplifier needs to be set on as high a frequency side as possible.
Furthermore, PSRR (power supply voltage rejection ratio) is named as an important factor for the high speed operation of the voltage regulator. To improve the PSRR characteristics, there is need to increase the total gain of the voltage regulator. In order to keep the phase margin adequate and, at the same time, increase the total gain, it is necessary to render the pole frequency of the 1st amplifier even higher. However, it is very difficult to control the pole of the 1st amplifier by the total gain.
With the aforementioned power circuit, on the other hand, it is common practice to create a zero-point frequency fzcl by the capacitance (CL) of the output capacitor CL and the resistance component (RESR) of the equivalent series resistance ESR, and carry out phase compensation based thereon.
The zero-point frequency fzcl in this case is expressed by the following equation (6):
                    fzcl        =                  1                      2            ⁢            π            ×            CL            ×            RESR                                              (        6        )            
As the above equation (6) shows, when a ceramic capacitor or the like, which is a low ESR capacitor, is used as the output capacitor CL, the zero-point frequency fzcl is high, and may be higher than a frequency which requires phase compensation. Therefore, the ceramic capacitor, if unchanged, may be unusable.
A tantalum capacitor or an electrolytic capacitor is known as the output capacitor Cl which can bring the zero-point frequency fzcl into a predetermined frequency region, and which is not a low ESR capacitor.
However, if the output capacitor CL having a large resistance component (RESR), such as a tantalum capacitor or an electrolytic capacitor, is used, a great ripple component is contained in the output voltage VOUT of the power circuit.
In earlier technologies, therefore, a ceramic capacitor with low ESR is used as the output capacitor CL, and a current feedback is given to make up for phase compensation which becomes inadequate because the equivalent series resistance component RESR is decreased in this case. Alternatively, the total gain is decreased to deteriorate overall performance, thereby coping with the problem.
FIGS. 16A and 16B are circuit diagrams showing phase compensation circuits each using a current feedback circuit. As shown in these drawings, if a low ESR ceramic capacitor is used as the output capacitor CL (see FIG. 11), current feedback 9 is performed for compensating for phase compensation which is inadequate because of low RESR. At this time, a summing circuit 10 is added to the output side of the error amplifier 1. As a result of this addition, the scale of the circuit grows, posing the problems of an increase in the chip area, and an increase in the number of the circuit elements, leading to increased current consumption.
A document teaching publicly known technologies concerned with the present invention is, for example, as follows:
Japanese Patent application Laid-Open No. 2004-153724.
As described above, power circuits generally perform phase compensation by utilizing the ESR of the output capacitor CL. If the capacitor of low ESR, which makes inadequate phase compensation, is used, a complicated circuit for current feedback 9 needs to be added in order to stabilize the system.